1. Field of the Invention
The present invention is related to semiconductor manufacturing. More specifically, the present invention is related to a method and apparatus for determining an assist feature placement in a layout using a process-sensitivity model.
2. Related Art
The dramatic improvements in semiconductor integration densities in recent years have largely been made possible by corresponding improvements in semiconductor manufacturing technologies.
One such semiconductor manufacturing technology involves placing assist features in a mask layout. Assist features (AFs) can be printing (e.g., super-resolution assist features) or non-printing (e.g., sub-resolution assist features). In either case, assist features are meant to improve the depth of focus of the patterns on the mask layout intended to be printed on the wafer.
Prior art techniques for placing assist features typically use mask rules, which place and cleanup assist features based on combinations of feature width and spacing parameters. Such rule-based approaches can result in missed or sub-optimal placement and/or cleanup of assist features. Further, the complexity of such rules increases rapidly with shrinking features size, thereby requiring more wafer data for calibration and more effort on the part of engineers. Moreover, these rules can be overly restrictive which can prevent designers from being able to achieve the best semiconductor device performance.
Furthermore, prior art techniques are typically directed towards improving manufacturability of 1-D patterns. As a result, these techniques are usually not effective for improving the depth of focus of 2-D patterns. In other words, prior art techniques are usually not directed towards optimizing the assist feature placement for improving depth of focus for 2-D patterns.
Hence, what is needed is a method and apparatus for determining an assist feature placement to improve the depth of focus for a layout, especially in regions with complex 2-D patterns.